[LinuxPPS] Ultimate time server

[Cirilo Bernardo]

On Wed, Dec 29, 2010 at 7:24 AM, Javier Herrero <jherrero at hvsistemas.es> wrote:

[snip]

> I've been playing a bit with a Blackfin board, with uClinux, and using
> an external FPGA counter to derive the system clock and to timestamp the
> PPS signal from the GPS (a M12T), with a resolution of 2.5ns (FPGA
> counters running at 400MHz). The 400MHz is derived from a 25MHz TCXO
> with <0.5ppm absolute frequency error (far better that any common PC
> clock). But results for now are not as good as I was expecting, probably
> due to the conversion from raw timestamp counts to time. Timestamps from
> the GPS shows jumps in the order of 200-300ns, and there is also a slow
> drift of +/-2us  that probably is due to oscillator wandering (a drift
> of 0.0625ppm would cause 1 microsecond error in 16 seconds).
>

That sounds like a fun project, especially if you can change the
programming of the FPGAs to make them do other neat tricks.  Keep in
mind that the GPS PPS signal is not necessarily well disciplined
either; for some cheap receivers the error is unspecified if the unit
is not stationary, and for some even when they are locked they are
only good to ~2us. I think you have close to the best performance that
you can reasonably expect from a TCXO. 5.4 milliseconds per day
(without further external time sources) is not necessarily bad.

 In the case of a Rb clock, once it is somehow referenced to an
absolute time the drift per day is very small and the Rb clock can be
used to tell if the GPS PPS is behaving (in which case you can use the
information to improve your offset from absolute time). A good GPS
data sheet will give you an estimate of the propagation time from
antenna jack until the PPS signal reaches 90% of its peak (or 10% for
an inverted signal) as well as the transition time of the PPS signal;
assuming no multi-pathing for the GPS signal, the additional delay
through the antenna lead and within the active antenna are easy to
calculate. The remaining error will be in the atmospheric propagation
time.

Did you implement a dual counter + latched readout on the FPGA to
avoid errors in reading the PPS timestamp counter? If you only have a
single counter then you must use a buffer (register) as well and also
ensure that you don't lose a clock pulse (count) while resetting the
counter. Personally I'm lazy and will use 2 counters.